Circuit Techniques for Power - Aware Microprocessors by O Ğ Uz Erg İ

Energy dissipation of the superscalar microprocessors increases drastically with increasing clock frequencies and increasing number of transistors. Reducing energy dissipation of a processor is important for further pushing performance and to avoid increasing cooling costs. In this thesis we introduce dissipate-on-match comparators and present zero-byte encoding to reduce energy dissipation in the superscalar datapath. Modern superscalar datapaths use aggressive execution reordering to exploit instruction level parallelism (ILP). Comparators, either explicit or embedded into contentaddressable logic, are used extensively throughout such designs to implement several key out-of-order execution mechanisms and support the memory hierarchy. The traditional comparator designs dissipate energy on a mismatch in any bit position. As mismatches occur with a much higher frequency than matches in many situations, considerable improvements in energy dissipation can be gained by using comparators that dissipate energy predominantly on a full match and dissipate little or no energy on partial or complete mismatches. We introduce a series of dissipate-on-match comparator designs, including designs for comparing long arguments. Further we show how comparators, used in modern datapaths, can be chosen and organized judiciously based on the microarchitectural-level statistics to minimize the energy dissipation. We use the actual layout data and realistic bit patterns of the comparands (obtained from the simulated execution of SPEC 2000